1. Technical Field
The present invention relates to an improved method and system for data processing in general and, in particular, to an improved method and system for processing data related to an integrated-circuit design. Still more particularly, the present invention relates to a method and system of checking for open circuit connections within an integrated-circuit design which is implemented with a hierarchial data structure.
2. Description of the Prior Art
Development of an integrated-circuit (IC) chip is a process that involves drafting a design specification, creating a logical design of the chip from the specification (typically in schematic form), checking the design, redesigning as necessary, fabricating the chip and testing the chip. Because of the increasing chip complexity, a design methodology commonly utilized today is macro-based, hierarchical, and top-down (or bottom-up). Under the macro-based design approach, a collection of circuits that forms a function or has a high connectivity is placed and wired together to form a macro. Two or more macros may be placed and wired together to form a super-macro. Finally, all super-macros are connected to each other to form an IC chip. This macro-based approach can support many levels of circuit hierarchy. In conjunction with the hierarchical design approach, many circuits within the IC chip may be designed in parallel. This reduces the chip design turnaround-time and makes reusable macros become feasible. In addition, the hierarchical design approach also minimizes the complexity and data volume of chip design at every level of circuit hierarchy. Under the top-down design approach, the planning starts at the highest level and progresses toward lower levels of the circuit hierarchy. The upper level defines the requirements of the design for the lower levels. Once the planning is complete, the design of the higher and lower levels can start in parallel to minimize the design cycle.
After the completion of the logical and physical design of the IC chip, the result of the design must be validated. Design validation requires thorough examination of the entire IC design and expected functional characteristics, taking into account a number of different factors, such as logical correctness of the design, timing factors (including wire delay, power dissipation, effects of parasitic capacitances, etc.). Because of the complexity of the IC design, virtually all design validations are performed by semiconductor design automation systems. These semiconductor design automation systems facilitate the capture, simulation, layout, and verification of IC chip designs.
A semiconductor design automation system typically operates in a hierarchical mode, by folding a previously processed circuit level into a current circuit level. One of the specifications of an IC chip design from within a semiconductor design automation system is a "net-list" that contains a complete description of all of the devices (e.g., transistors, resistors, etc.) required and how each of the devices is connected. Specifically, each connection within the IC chip design is described in the form of a "net" (short for "network") or in the form of point-to-point wiring connections between devices. A single net may connect to many devices, and a net-list includes a list of all net interconnections, thus the name "net-list." A semiconductor design automation system analyzes each net and categorizes how each net spans the hierarchy of the total design.
With reference now to the drawings, and specifically to FIG. 1, there is illustrated a block diagram of a net of a circuit design. As shown, net 10 has two levels, namely, a parent circuit level 11 and a child circuit level 12. Looking from child circuit level 12, net 10 appears to have an "open" at connections 13 and 14. Hierarchical processing typically requires a net to be completely connected in each circuit level, so that network continuity is assured when all the pieces are brought together. Hence, child circuit level 12 of net 10 as shown in FIG. 1 will be considered as having an open circuit connection by the semiconductor design automation system.
As a general rule, any open circuit connection in a net should be flagged. However, sometimes an IC chip designer may need some flexibility to this "generic" open circuit checking rule, usually related to a routing requirement. Hence, a method is needed to somehow indicate to the semiconductor design automation system that, for a specific portion of a given hierarchical net, an open circuit connection is intended and permissible. Yet, at the same time, the design automation system must be able to catch a true open connection in the wiring of the circuit. Consequently, it would be desirable to provide an improved method and system of checking for open circuit connections within an integrated-circuit design that is represented by a hierarchial data structure.